1. Field of the Invention
The invention relates to microprocessors and more particularly, in such microprocessors, to a system for organizing the electronic circuits and a method for sequencing the operations performed by these circuits so as to increase the efficiency of the circuits in terms of speed and reduction of electrical consumption.
In a microprocessor, the different instructions of a program are implemented sequentially by periodic electrical signals provided by a clock circuit. The number of cycles of the clock signals needed to perform one instruction varies from one microprocessor to another depending on the manufacturer and type of microprocessor. This number ranges from some cycles to several tens of cycles.
Consequently, microprocessor manufacturers have sought to reduce the number of cycles per instruction to the utmost. This has meant lowering the frequency of the clock signals for a given level of efficiency and, correlatively, reducing the electrical consumption which varies in the same way as the frequency.
2. Description of the Prior Art
At present, the most powerful microprocessors perform an instruction in one half-cycle. However, to achieve a performance level of this kind, they use the techniques known as "pipelining" and "parallelism". Thus, for example, an instruction is performed in four cycles but during these very same cycles, eight other instructions will be performed in parallel.
Techniques of this kind have the following drawbacks:
the pipelining technique is easy to manage during the running of a linear program but very difficult to manage when a program contains many "conditional branches" or "conditional jumps", which is the most usual case. For, should there be a conditional branch, the other instructions loaded into the pipeline structure would not be performed. It would therefore become necessary to fill the pipeline structure again, entailing a great loss of efficiency; PA1 an architecture of this kind leads to a greater complexity and to an increase in the volume of the hardware used: this does not make for a sound compromise between the surface area of the integrated circuits and the efficiency of the unit; PA1 an architecture of this kind, following the loss of efficiency due to the pipeline structure and the increase in the volume of hardware leads to a greater electrical consumption. PA1 the input terminals of said inhibiting device being connected to the input terminals of the associated register, to the second output terminal of the preceding inhibiting device and to an output terminal of the clock circuit, PA1 the first output terminal of the inhibiting device being connected to the clock signal input terminal of the associated instruction register, PA1 the inhibiting device being designed to provide, at the first output terminal, a signal for the loading of the associated instruction register when the instruction code contains a predetermined combination of digits.
The object of the present invention therefore is to achieve a system for organizing the electronic circuits of a microprocessor and a method of sequencing the operations performed by these circuits resulting in greater efficiency of the microprocessor, namely in a small number of clock cycles per instruction, a small cycle period, namely a high clock frequency and a low electrical consumption.